The present invention generally relates to a semiconductor memory apparatus for and writing data at random.
Semiconductor memory device for reading and writing data at random, especially dynamic random access memories (DRAMs), have been widely used in the recent years due to their mass memory capacity and lower cost, and it is expected that the memory capacity and performance capabilities of such devices will increase year by year.
A multiplexing bit line system is proposed as one technique of achieving higher performance (higher speed) of the DRAM (T. Mano et al., "Circuit Technologies for 16 Mb DRAMs" ISSCC87 Digest of technical papers, P22 (February, 1987)).
FIGS. 9 and 10 show the construction of the conventional multiplexing bit line system. In FIG. 9, reference numeral 101 denotes unit memory cells each constructed of one transistor TR and one capacitor CS being provided as shown in FIG. 10. In FIG. 9, reference numeral 102 denotes word lines for selecting a row of the memory cell 101 and being connected to the gate of each transistor TR as shown in FIG. 10. In FIG. 9, reference numeral 103 denotes bit lines for reading and writing data directly from and to each memory cell 101, and is connected with the drain of each transistor TR as shown in FIG. 10.
As shown in FIG. 9, a sense amplifier SA for amplifying the micropotential on the bit line 103 is connected with a pair of bit lines 103. Each upper bit line 106 is connected through a switch element 104 which controls according to a signal line 105 the selection of a block including the memory cells 101 connected with the end portion of each bit line 103. In the following, the bit line 106 is referred to as an upper bit line 106 and the bit line 103 is referred to as a lower bit line 103.
A main amplifier MA is connected with a pair of upper bit lines 106 so as to amplify the micropotential on the upper bit line 106. A common data line pair 108 is connected with the end portion of each upper bit line 106 through a switch element 107 to be controlled by a string decoder YS for selecting the string direction of the memory cell 101. In this case, a pair of common data lines 108 is connected with respect to a plurality of pairs of upper bit lines 106.
FIG. 11 shows a basic construction of a data line orthogonal system DRAM which is different from the conventional multiplexing bit line system described hereinabove. In FIG. 11, reference numeral 201 denotes unit memory cells, reference numeral 202 denotes word lines for selecting the row direction of the memory cell 201 and reference numeral 203 denotes bit lines for reading and writing data directly from and to each memory cell 201, with no distinction being provided between the upper and the lower in the bit line 203.
A sense amplifier SA is connected with a pair of bit lines 203 so as to amplify the micropotential on the bit lines 203, and also, a switch element 204 to be controlled by a string decoder YS for selecting the string direction of the memory cell 201 is connected with the end portion of each bit line 203. Also, a pair of common data lines 208 is connected with respect to a plurality of pairs of bit lines 203.
The multiplexing bit line system has an advantage of a having higher speed property as compared with the data line orthogonal system. This is due to the difference in the floating capacity of the data line of the rear stage of the sense amplifier SA.
The timing of connecting a bit line to be connected with a memory cell with a data line of the rear stage of the sense amplifier SA is faster if the capacity of the data line of the rear stage of the sense amplifier SA is smaller. As the floating capacity in the data line of the rear stage of the sense amplifier SA is smaller, the higher speed may be effected. The data line of the rear stage of the sense amplifier SA is an upper bit line 106 in the multiplexing bit line system, and is a common data line pair 208 in the data line orthogonal system. The capacity component of the upper bit line 106 is mainly a wiring capacity, while the capacity component of the common data line pair 208 is a wiring capacity and a diffusion capacity of the drain region of the switch element 204. As the common data line pair 208 is normally two to three times as large as in floating capacity, the multiplexing bit line system has the higher speed performance.
But in the construction of such a multiplexing bit line system as described hereinabove, the upper bit lines of 2048 through 4096 are operated at the same time in the 16M bit class. Namely, the electric charge is charged to and discharged from the power voltage level or the ground level with the respect to several thousands of lines of wiring capacity.
In the data line orthogonal system, four through sixteen lines of common data line pairs are operated also in the 16M bit class so as to charge or discharge the electric charge.
It is clearly found in both systems that the multiplexing bit line system is larger as compared with the size of capacity to be charged to and discharged from at the same time. This means that the multiplexing bit line system has a disadvantageously larger consumption current.